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| (R) HA5351 Data Sheet April 12, 2007 FN3690.10 64ns Sample and Hold Amplifier The HA5351 is a fast acquisition, wide bandwidth sample and hold amplifier, built with the Intersil HBC-10 BiCMOS process. This sample and hold amplifier offers a combination of desirable features; fast acquisition time (70ns to 0.01% maximum), excellent DC precision and extremely low power dissipation, making it ideal for use in systems that sample multiple signals and require low power. The HA5351 is in an open loop configuration with fully differential inputs providing flexibility for user defined feedback. In unity gain the HA5351 is completely self-contained and requires no external components. The on-chip 15pF hold capacitor is completely isolated to minimizing droop rate and reducing sensitivity to pedestal error. The HA5351 is available in 8 lead SOIC package for minimizing board space and ease of layout. Features * Fast Acquisition to 0.01%. . . . . . . . . . . . . . . . . 70ns (Max) * Low Offset Error . . . . . . . . . . . . . . . . . . . . . . . 2mV (Max) * Low Pedestal Error. . . . . . . . . . . . . . . . . . . . 10mV (Max) * Low Droop Rate . . . . . . . . . . . . . . . . . . . . . . 2V/s (Max) * Wide Unity Gain Bandwidth . . . . . . . . . . . . . . . . . . 40MHz * Low Power Dissipation . . . . . . . . . . . . . . . .220mW (Max) * Total Harmonic Distortion (Hold Mode) . . . . . . . . . -72dBc - (VIN = 5VP-P at 1MHz) * Fully Differential Inputs * On Chip Hold Capacitor * Pb-Free Plus Anneal Available (RoHS Compliant) Ordering Information PART NUMBER HA5351IB HA5351IBZ (Note) PART MARKING 5351 I 5351 IBZ TEMP. RANGE (C) -40 to +85 -40 to +85 PACKAGE 8 Ld SOIC 8 Ld SOIC (Pb-free) PKG. DWG. # M8.15 M8.15 Applications * Synchronous Sampling * Wide Bandwidth A/D Conversion * Deglitching * Peak Detection * High Speed DC Restore NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Pinout HA5351 (8 LD SOIC) TOP VIEW +IN 1 2 3 4 8 7 6 5 -IN GND V+ S/H CTRL Functional Diagram V+ 6 V3 15pF 8 + GM 1 +IN 5 BUFFER HA5351 7 GND + NC VOUT -IN AV 4 OUT S/H 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003, 2006, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HA5351 Absolute Maximum Ratings Voltage Between V+ and V- Terminals. . . . . . . . . . . . . . . . . . . .+11V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V Voltage Between Sample and Hold Control and Ground. . . . . +5.5V Output Current, Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . 37mA Thermal Information Thermal Resistance (Typical, Note 1) JA (C/W) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Maximum Junction Temperature (Plastic Package) . . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . -65C to +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Test Conditions: VSUPPLY = 5V; CH = Internal = 15pF, Digital Input: VIL = 0V (Sample), VIH = 4.0V (Hold). Non-Inverting Unity Gain Configuration (Output Tied to -Input), CL = 5pF, Unless Otherwise Specified TEST CONDITIONS TEMP. (C) Full 25 25 25 Full Full Full Full Full 2.5V, Note 3 VOUT = 2.5V Full 25 Full 25 200mV Step 200mV Step 5V Step VIH VIL 25 25 Full 25, 85 -40 Full Full Full Full 25, 85 -40 Full 25 25 25 MIN -2.5 100 -2 -3.0 -1.5 -2.5 60 95 85 0 88 2.1 2.4 0 -1.0 -1.0 -3.0 20 15 TYP 500 15 2.5 80 108 40 8.5 105 25 13 0.02 325 325 MAX +2.5 5 2 3.0 5 +1.5 +2.5 30 5.0 5.0 0.8 1.0 1.0 +3.0 UNITS V k pF mV mV V/C A A V dB dB dB MHz ns % V/s V V V A A V mA mA MHz VRMS VRMS PARAMETER INPUT CHARACTERISTICS Input Voltage Range Input Resistance (Note 2) Input Capacitance Input Offset Voltage Offset Voltage Temperature Coefficient Bias Current Offset Current Common Mode Range Common Mode Rejection Ratio TRANSFER CHARACTERISTICS Large Signal Voltage Gain Unity Gain -3dB Bandwidth TRANSIENT RESPONSE Rise Time Overshoot Slew Rate DIGITAL INPUT CHARACTERISTICS Input Voltage Input Current OUTPUT CHARACTERISTICS Output Voltage Output Current Full Power Bandwidth Output Resistance Total Output Noise (DC to 10MHz) VIL = 0V VIH = 5V RL = 510 RL = 100 5VP-P, AV = +1, -3dB Hold Mode Sample Mode Hold Mode 2 FN3690.10 April 12, 2007 HA5351 Electrical Specifications Test Conditions: VSUPPLY = 5V; CH = Internal = 15pF, Digital Input: VIL = 0V (Sample), VIH = 4.0V (Hold). Non-Inverting Unity Gain Configuration (Output Tied to -Input), CL = 5pF, Unless Otherwise Specified (Continued) TEST CONDITIONS TEMP. (C) MIN TYP MAX UNITS PARAMETER DISTORTION CHARACTERISTICS SAMPLE MODE Total Harmonic Distortion VIN = 4.5VP-P, fIN = 100kHz VIN = 5VP-P, fIN = 1MHz VIN = 1VP-P, fIN = 10MHz 25 25 25 25 - -80 -74 -57 73 - dBc dBc dBc dB Signal to Noise Ratio (RMS Signal to RMS Noise) HOLD MODE (50% Duty Cycle S/H) Total Harmonic Distortion VIN = 4.5VP-P, fIN = 100kHz VIN = 4.5VP-P, fIN = 100kHz, fS 100kHz VIN = 5VP-P, fIN = 1MHz, fS 1MHz VIN = 1VP-P, fIN = 10MHz, fS 1MHz 25 25 25 25 - -78 -72 -51 70 - dBc dBc dBc dB Signal to Noise Ratio (RMS Signal to RMS Noise) SAMPLE AND HOLD CHARACTERISTICS Acquisition Time VIN = 4.5VP-P, fIN = 100kHz, fS 100kHz 0V to 2.0V Step to 1mV 0V to 2.0V Step to 0.01% (200V) -2.5V to +2.5V Step to 0.01% (500V) 25 25 25 25 Full -2 -10 60 53 64 90 0.3 50 72 +1 10 10 20 20 74 70 100 2 +10 20 22 22 - ns ns ns V/s V/s mV ns dB ns ns ps mA mA dB Droop Rate Hold Step Error Hold Mode Settling Time Hold Mode Feedthrough EADT (Effective Aperture Delay Time) Aperture Time (Note 2) Aperture Uncertainty POWER SUPPLY CHARACTERISTICS Positive Supply Current Negative Supply Current PSRR NOTES: 2. Derived from Computer Simulation only, not tested. 3. +CMRR is measured from 0V to +2.5V, -CMRR is measured from 0V to -2.5V. 10% Delta VIL = 0V, VIH = 4.0V, tR = 5ns To 1mV 5VP-P, 500kHz, Sine Full 25 25 25 25 25 Full Full Full 3 FN3690.10 April 12, 2007 HA5351 Typical Performance Curves 2 OUTPUT (V) OUTPUT (V) 0 100 200 300 TIME (ns) 400 500 0.1 0 0.0 -2 -0.1 200 400 TIME (ns) 600 FIGURE 1. LARGE SIGNAL RESPONSE FIGURE 2. SMALL SIGNAL RESPONSE 2 60 0 40 GAIN (dB) 40.163156MHz -3dB GAIN (dB) -2 GAIN 0dB AT 21.34MHz 20 0 -30 -60 0 -6 -20 -8 100k 1M 10M 100M 1k 10k 100k PHASE -119.86 1M 10M -90 -120 -150 -180 100M PHASE () 6 -4 FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 3. UNITY GAIN FREQUENCY RESPONSE FIGURE 4. CLOSED LOOP GAIN/PHASE AV = +1000 2 60 200mVP-P -3dB BANDWIDTH (MHz) 50 13.241189MHz -3dB 40 30 20 10 0 3.5 4 TYPICAL UNITS 0 GAIN (dB) -2 -4 -6 -8 10k 100k 1M FREQUENCY (Hz) 10M 100M 4 4.5 5 SUPPLY VOLTAGE (V) 5.5 FIGURE 5. 5VP-P FULL POWER FREQUENCY RESPONSE FIGURE 6. -3dB BANDWIDTH vs SUPPLY VOLTAGE 4 FN3690.10 April 12, 2007 HA5351 Typical Performance Curves (Continued) 0.5 3 TYPICAL UNITS 150 0.4 DROOP RATE (V/s) SLEW RATE (V/s) 140 130 120 110 100 90 0 -50 80 -50 UNIT #2 UNIT #3 160 3 TYPICAL UNITS +SLEW RATE -SLEW RATE UNIT #1 0.3 0.2 0.1 0 50 TEMPERATURE (C) 100 0 50 TEMPERATURE (C) 100 FIGURE 7. DROOP RATE vs TEMPERATURE FIGURE 8. SLEW RATE vs TEMPERATURE 9 65 4 TYPICAL UNITS HOLD MODE SETTLING TIME (ns) 60 55 50 45 40 35 30 -50 4 TYPICAL UNITS 8 RISE TIME (ns) 7 6 5 4 -50 0 50 TEMPERATURE (C) 100 0 50 TEMPERATURE (C) 100 FIGURE 9. RISE TIME vs TEMPERATURE FIGURE 10. HOLD MODE SETTLING vs TEMPERATURE 3 0V TO 4V S/H CTRL 2 PEDESTAL ERROR (mV) OUTPUT OUTPUT (V) 1 S/H CONTROL (V) 0.01 10 0.00 S/H CONTROL 67.25ns 0 5 -1 -0.01 0 10 20 30 40 50 0 -2 3.0E-7 TIME (ns) S/H CONTROL RISE TIME (ns) FIGURE 11. PEDESTAL vs S/H CONTROL RISE TIME FIGURE 12. ACQUISITION TIME (0.01%, 0V TO 2V STEP) 5 FN3690.10 April 12, 2007 HA5351 Typical Performance Curves (Continued) OUTPUT 0.02 10 OUTPUT (V) S/H CONTROL (V) 0.00 -0.02 5 -0.04 51.4 ns 0 0 20 40 TIME (ns) 60 80 FIGURE 13. HOLD MODE SETTLING TIME (200V) Die Characteristics SUBSTRATE POTENTIAL: VTRANSISTOR COUNT: 156 Metallization Mask Layout HA5351 GND GND GND V+ V+ V+ S/H CONTROL -IN VOUT VOUT +IN V- V- V- 6 FN3690.10 April 12, 2007 HA5351 Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45 H 0.25(0.010) M BM M8.15 (JEDEC MS-012-AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 L MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 5.80 0.25 0.40 8 8 0 8 MAX 1.75 0.25 0.51 0.25 5.00 4.00 6.20 0.50 1.27 NOTES 9 3 4 5 6 7 Rev. 1 6/05 MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497 0.2284 0.0099 0.016 8 0 MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574 0.2440 0.0196 0.050 B C D E A1 0.10(0.004) C e H h L N 0.050 BSC 1.27 BSC e B 0.25(0.010) M C AM BS NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 7 FN3690.10 April 12, 2007 |
Price & Availability of HA535107
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